1. Technical Field
The present invention relates in general to an improved integrated circuit design method and in particular to an improved integrated circuit design method for optimum insertion of buffers in an integrated circuit containing single-sink and multi-sink circuits. Still more particularly, the present invention relates to a design method which determines an optimum distance from a sink in multi-sink circuits for a buffer location and generates candidate solutions and selects optimum buffer locations from the candidate locations.
2. Description of the Related Art
Often, when a signal propagates within an integrated circuit noise is induced into the signal. The signal can be restored to its original shape by "repowering" the signal utilizing simple amplifiers called "buffers".
In designing an integrated circuit, the physical layout is accomplished in view of all the pertinent design constraints. Generally, after the layout or geographical planning of a semiconductor chip is complete, noise considerations are then addressed or considered. Development of faster and larger integrated circuits has created the need for effective and efficient computer aided design (CAD) tools for the design of such circuits.
The most desirable computer assistance comes in the form of calculations on circuit models to identify potential problems such as unacceptable delays and excessive noise. An area of integrated circuit design which has received additional attention recently is the prediction of noise in high frequency dynamic logic circuits. The rapid development of higher clock frequencies has intensified the effort to develop CAD assistance for the design of such circuits.
Avoiding problems created by noise through noise analysis is a critical step in sub-micron integrated circuit design. Ever increasing requirements for integrated circuit performance have led to widespread utilization of dynamic logic circuit families and derivatives of dynamic logic families in integrated circuits. Dynamic logic families are aggressive circuit families, which trade noise margin for timing performance. Therefore, dynamic logic families are more susceptible to noise failure than conventional static logic. The re is an eve r increasing need for noise analysis methods and buffer insertion to avoid noise failures.
Currently three popular methods for noise analysis are prevalent, including circuit simulation, timing simulation, and model order reduction. Even though these techniques are adequate for analysis they cannot be utilized to optimize a design. Further, effective buffer insertion to compensate for noise problems in on-chip interconnects is presently a topic of intense investigation.
With increasing operating frequencies, noise analysis and interference prevention are becoming more important in the integrated circuit design process. Advances in process technology have allowed a substantial reduction in the minimum distance between adjacent conductors in an integrated circuit. Closer proximity of conductors in an integrated circuit produces increased coupling capacitance between a conductor and adjacent conductors.
Integrated circuit design constraints dictate that the distance between two conductors in an integrated circuit can be reduced more than the height of the conductor. Thus, the height of a conductor on an integrated circuit is typically greater than the width of the conductor. The aspect ratio of each conductor and corresponding parallel surface area between two conductors causes an in crease in the ratio of coupling capacitance to ground plane capacitance.
For present day integrated circuits, the ratio of coupling capacitance to ground plane capacitance can be as high as thirty five percent. As a result of the increase in the coupling capacitance, a transient voltage or current on a conductor can adversely affect neighboring signals.
If a circuit or net is quiet, a neighboring "aggressor" circuit may be active and a switching signal on the aggressor net can induce a noise pulse in the quiet circuit or "victim circuit". This phenomenon can have a detrimental effect on circuit response. For example, a coupled noise pulse can erroneously switch the state of a transistor which is required to be in a different state. Undesired switching of a single transistor can "lock up" an entire computer system rendering the computer system unresponsive to all input.
Today's manufacturing techniques allow the threshold voltage of a transistor to be close to zero volts. Low switching threshold voltages make prevention of faulty switching of a transistor due to coupling noise a significant concern.
Dynamic logic circuits trade "noise margin" or susceptibility to noise for faster switching, reduced circuit delay, and ultimately faster operating speed. Presently, greater utilization of noise analysis in the design phase of integrated circuits having dynamic logic families is required due to the reduced noise margin and increased noise susceptibility.
Changing the capacitive coupling within an integrated circuit generally requires rewiring the integrated circuit to change the location of conductors on the chip. If a noise problem goes undetected to the fabrication stage, correcting the noise problem will require an expensive second fabrication run.
Many CAD delay calculations utilize the "Elmore" delay model to analyze circuits. The Elmore model is named after the works of W. C. Elmore. The basis of the Elmore model can be found in an article entitled "The Transient Response of Damped Linear Networks with Particular Regard to Wide-Band Amplifiers," W. C. Elmore J. Appl. Phys., vol. 1, no. 1, pp. 55-63, Jan. 1948.
The Elmore delay model and its derivatives have been utilized extensively for buffer insertion designs. The Elmore delay model is popular because it is a "top-down" analysis.
Another important factor in utilizing the Elmore delay model, is that the complexity of computing the delay has a linear relationship to the number of receiving circuits and therefore the calculation can be performed efficiently. The Elmore delay theory has been widely utilized by CAD developers for computer aided insertion of buffers into circuits.
For example, "Buffer Placement in Distributed RC-Tree Networks for Minimal Elmore Delay", by Lukas P. P. P. van Ginneken, (Lukas van Ginneken) Proc. Intern'l Symposium on Circuits and Systems, 1990, pp. 865-868, proposed a solution for buffer insertion to minimize Elmore delay.
Lukas van Ginneken's method is severely limited because only one buffer can be placed on a single conductor. This leads to solutions which have an inadequate quantity of buffers in most designs. For example, a fan-out tree which requires three buffers for optimum performance may receive only one buffer utilizing Lukas van Ginneken's method. Further, the device library of Lukas van Ginneken's proposal includes only one non-inverting buffer. A single device library also severely limits the effectiveness of the Lukas van Ginneken method by limiting candidate solutions.
Lillis et al. (Lillis) proposed many improvements to Lukas van Ginneken's approach, adding the functionalities of conductor sizing, a non-unit buffer library and inverting buffers. The Lillis approach also incorporated slew into the gate delay calculation. Lillis subdivided conductors into infinitesimally small segments to overcome the onerous problem of Lukas van Ginneken that only one buffer can be inserted on each conductor.
However, in utilizing the Lillis method, the processing speed for each conductor becomes inordinately slow due to the endless topologies which must be considered by the CAD system. Therefore, the processing speed utilizing the Lillis method on a given tree is too slow and inefficient for most applications. However, the Lillis approach provides many enhancements and an improved solution to the Lukas van Ginneken's method. Again, Lillis' model is too slow and inefficient for most applications.
Noise avoidance techniques must become an integral part of the performance optimization environment. It should therefore be apparent that a buffer insertion tool providing a suitable environment for optimization of noise is needed.